With development of Ethernet interconnection and InfiniBand technologies, an interconnection system of a PCIe Fabric formed based on peripheral component interconnect express (PCIe) has appeared. The interconnection system of the PCIe Fabric, also referred to as a PCIe interconnection system, generally includes one management node and N working nodes, each node belongs to an independent domain, and the connection and the address isolation between different domains are implemented using a non-transparent bridge (NTB) A peripheral component interconnect express input/output (PCIe I/O) device provided to and shared by each working node is usually set in a domain in which the management node is located.
In a system based on a PCIe Fabric interconnection structure, a domain in which a working node is located and a domain in which the PCIe I/O device is located implement address isolation by using the NTB. To enable the working node to use the PCIe I/O device, configuration initialization needs to be performed on the NTB, so that the working node manages the PCIe I/O device, and a message-signaled interrupts extended (MSI-X) interrupt of the PCIe I/O device is transmitted from the domain in which the management node is located to the domain in which the working node is located.
In the prior art, to share a shared PCIe I/O device, each base address register (BAR) at a working node side of the NTB needs to be mapped to one control and status register (CSR) of a device; and a BAR at a management node side of the NTB needs to be mapped to a large continuous memory area used as an memory area for receiving an MSI-X message.
After studying the prior art, the inventor finds that a size of a BAR corresponding to an NTB at each working node in a PCIe interconnection system is determined by a quantity of shared PCIe I/O devices, and needs to be set when the PCIe interconnection system is initialized, and when the PCIe interconnection system is initialized, it cannot be predicted that how many shared PCIe I/O devices needs to be used by the working node. If a relatively small BAR is set in hardware, when multiple PCIe I/O devices need to be used, all MSI-X interrupts of the PCIe I/O devices may not be transmitted to the working node by using the BAR; and if a relatively large BAR is set, an address conflict may occur in an MSI-X interrupt of a PCIe I/O device in a working node domain and an MSI-X interrupt of a shared PCIe I/O device. It can be seen from the foregoing content that, when an existing method is used to implement sharing of a PCIe I/O device, a size of a BAR is difficult to be determined when a PCIe interconnection system is initialized